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Overcoming the Barriers to Exascale through Innovation

Steve Pawlowski (Intel Senior Fellow & CTO Datacenter and Connected Systems Group)

In a period of just 20 years, the performance of the world’s fastest computers has increased by a factor of one million. Although in the past this was due above all to an increase in the processors’ clock frequency, today the performance of top systems is based on a gigantic number of processors operating in parallel. The next target exascale with a thousand times the performance of current systems requires a paradigm shift. The many millions or billions of processor cores must be synchronized, the reliability of the components must be guaranteed, and new storage technologies are required. A quite decisive part will be played by reducing energy consumption.
In his talk, Stephen S. Pawlowski will discuss the unique challenges posed by exascale computing as well as the laboratory partnerships that Intel is developing in the US and Europe. The four labs, including the ExaScience Lab in Leuven, collaborate closely on developing novel algorithms, system architectures and software tools to reach exascale.

The Fault-Tolerance for HPC at Extreme Scale (FTXS 2012) Workshop is solliciting submissions related to dealing with failures, from papers describing innovative ideas over experience reports to extended abstracts proposing disruptive ideas.

More details can be found on FTXS’s website, or in the call for papers in pdf or text formats. Feel free to distribute this information widely so we can get a lively workshop.

CALL FOR PAPERS

2nd International Workshop on Fault-Tolerance for HPC at Extreme Scale (FTXS 2012)

In conjunction with:
The 42nd Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN 2012), Boston, Massachusetts, USA on June 25-28, 2012.

WORKSHOP MOTIVATION

For the HPC community, a new scaling in numbers of processing elements has superseded the historical trend of Moore’s Law scaling in processor frequencies. This progression from single core to multi-core and many-core will be further complicated by the community’s immanent migration from traditional homogeneous architectures to ones that are heterogeneous in nature. As a consequence of these trends, the HPC community is facing rapid increases in the number, variety, and complexity of components, and must thus overcome increases in aggregate fault rates, fault diversity, and complexity of isolating root cause.

Recent analyses demonstrate that HPC systems experience simultaneous (often correlated) failures. In addition, statistical analyses suggest that silent soft errors can not be ignored anymore, because the increase of components, memory size and data paths (including networks) make the probability of silent data corruption (SDC) non-negligible. The HPC community has serious concerns regarding this issue and application users are less confident that they can rely on a correct answer to their computations. Other studies have indicated a growing divergence between failure rates experienced by applications and rates seen by the system hardware and software. At Exascale, some scenarios project failure rates reaching one failure per hour. This conflicts with the current checkpointing approach to fault tolerance that requires up to 30 minutes to restart a parallel execution on the largest systems.  Lastly, stabilization periods for the largest systems are already significant, and the possibility that these could increase in length is of great concern.  During the Approaching Exascale report at SC11, DOE program managers identified resilience as a black swan – the most difficult under-addressed issue facing HPC.

OPEN QUESTIONS

What does the fault-tolerance community need to do in order to be prepared to face the challenges of extreme scale computing? What is needed to keep applications with billions of threads of parallelism up and running on systems that fail tens of times per day? As models predict less than 50% efficiency of traditional checkpoint/restart methods on future systems, are we ready to pay the cost of full redundancy, effectively performing redundant multi-threading (RMT) across entire systems? Do we even have the infrastructure necessary to implement an RMT strategy?

How is the supercomputing community going to efficiently isolate failures on enormously complex systems? Is there any chance to understand these systems in such a way that some failure could be predicted with enough accuracy and anticipation to trigger useful failure avoidance actions? What can the community do to protect applications from SDC in memory and logic? How far the user and the programmer should be involved in managing faults? What are the most promising self-healing numerical methods?

GOALS

The goals of this workshop are to consider these complex questions, to discuss the unique limitations that extreme scale and complexity impose on traditional methods of fault-tolerance, and to explore new strategies for dealing with those challenges.

PAPER SUBMISSIONS

Submissions are solicited in the following categories:

• Regular papers presenting innovative ideas improving the state of the art.
• Experience papers discussing the issues seen on existing extreme-scale systems, including some form of analysis and evaluation.
• Extended abstracts proposing disruptive ideas in the field, including some form of preliminary results

Submissions shall be sent electronically, must conform to IEEE conference proceedings style and should not exceed six pages including all text, appendices, and figures.

All papers will be published, as workshop papers, in the DSN 2012 proceedings and on IEEE Xplore.

TOPICS

Assuming hardware and software errors will be inescapable at extreme
scale, this workshop will consider aspects of fault tolerance peculiar
to extreme scale that include, but are not limited to:

• Quantitative assessments of cost in terms of power, performance, and resource impacts of fault-tolerant techniques, such as checkpoint restart, that are redundant in space, time or information
• Novel fault-tolerance techniques and implementations of emerging hardware and software technologies that guard against silent data corruption (SDC) in memory, logic, and storage and provide end-to-end data integrity for running applications; Studies of hardware / software tradeoffs in error detection, failure prediction, error preemption, and recovery
• Advances in monitoring, analysis, and control of highly complex systems
• Highly scalable fault-tolerant programming models
• Metrics and standards for measuring, improving and enforcing the need for and effectiveness of fault-tolerance
• Failure modeling and scalable methods of reliability, availability, performability and failure prediction for fault-tolerant HPC systems
• Scalable Byzantine fault tolerance and security from single-fault and fail-silent violations
• Benchmarks and experimental environments, including fault-injection and accelerated lifetime testing, for evaluating performance of resilience techniques under stress

IMPORTANT DATES

Submission of papers:   March 16, 2012
Author notification:    April 6, 2012
Camera ready papers:    April 27, 2012
Workshop:               June 25, 2012

WORKSHOP ORGANIZERS

Nathan DeBardeleben – Los Alamos National Laboratory
Jon Stearley – Sandia National Laboratories
Franck Cappello – INRIA & University of Illinois at Urbana Champaign

PROGRAM COMMITTEE

George Bosilca – University of Tennessee, Knoxville
Greg Bronevetsky – Lawrence Livermore National Laboratory
John Daly – Department of Defense
Christian Engelmann – Oak Ridge National Laboratory
Kurt Ferreira – Sandia National Laboratories
Ana Gainaru – University of Illinois, Urbana-Champaign
Hideyiki Jitsumoto – University of Tokyo
Zbigniew Kalbarczyk – University of Illinois, Urbana-Champaign
Rakesh Kumar – University of Illinois, Urbana-Champaign
Zhiling Lan – Illinois Institute of Technology
Yve Robert – ENS Lyon
Roel Wuyts – Intel ExaScience Lab, Leuven, Belgium and KU Leuven (Leuven, Belgium)
Felix Salfner – SAP Innovation Center Potsdam
Mitsuhisa Sato – University of Tsukuba
Stephen Scott – Oak Ridge National Laboratory and Tennessee Tech University

See http://institute.lanl.gov/resilience/workshops/ftxs2012/
and http://2012.dsn.org for more information.

There will be a minisymposium organized by members of the lab on “Hardware/Software Co-design for High-performance Coupled Physics Simulations”.

Furthermore there will be 2 poster presentations, one on sparse matrix-vector multiplication by Albert-Jan Yzelman, the other on algebraic multigrid techniques by Pawan Kumar.

The talks on PP12 will be recorded! So check the PP12 website after the conference.

The Sniper simulator allows one to perform timing simulations for multi-threaded, shared-memory applications with 10s to 100+ cores, at a high speed when compared to existing simulators. The main feature of the simulator is its core model which is based on the interval core model, a fast mechanistic core model. The interval model raises the level of abstraction in architectural simulation which allows for faster simulator development and evaluation times; it does so by ‘jumping’ between miss events, called intervals. On recent multi-core hardware, we see simulation speeds up to 3 MIPS.

This simulator, and the interval core model, is useful for uncore and system-level studies that require more detail than the typical one-IPC models. As an added benefit, the interval core model allows the generation of CPI stacks, which show the number of cycles lost due to different characteristics of the system, like the cache hierarchy or branch predictor, and lead to a better understanding of each component’s effect on total system performance.

Visit http://snipersim.org for more information.

The full paper can be found in our publications section, but here is its abstract:

The basic building blocks of a classic multigrid algorithm, which are essentially stencil computations, all have a low ratio of executed floating point operations per byte fetched from memory. This important ratio can be identified as the arithmetic intensity. Applications with a low arithmetic intensity are typically bounded by memory traffic and achieve only a small percentage of the theoretical peak performance of the underlying hardware. We propose a polynomial Chebyshev smoother, which we implement using cache-aware tiling, to increase the arithmetic intensity of a multigrid V-cycle. This tiling approach involves a trade-off between redundant computations and cache misses. Unlike common conception, we observe optimal performance for higher degrees of the smoother. The higher degree polynomial Chebyshev smoother can be used to smooth more than just the upper half of the error frequencies, leading to better V-cycle convergence rates. Smoothing more than the upper half of the error spectrum allows a more aggressive coarsening approach where some levels in the multigrid hierarchy are skipped.

As usual, happy reading !

Przemyslaw Klosiewicz will be presenting a poster on “Increasing the computational intensity of stencil calculations: memory bandwidth vs CPU speed”.

You can now find this paper in our publication section. Happy reading!

We’ll tell you when the paper becomes available in the publications section, but in the meantime you can already have a look at the abstract that summarizes the work:

Optimizing parallel workloads is becoming increasingly important given the advent of multicore and manycore processors, and tools and methodologies for analyzing parallel performance are key to this endeavor. Software developers rely on analysis tools for identifying performance bottlenecks and optimizing software for both current and future hardware. Likewise, computer architects need performance analysis tools to understand workload behavior and drive future processor and system design.

This paper proposes a methodology for analyzing parallel performance by building cycle stacks. A cycle stack quantifies where the cycles have gone, and provides a hint towards optimization opportunities. We make the case that this is particularly interesting for analyzing parallel performance: understanding how cycle components scale with increasing core counts and/or input data set sizes leads to insight with respect to scaling bottlenecks due to synchronization, load imbalance, poor memory performance, etc. We present several case studies illustrating the use of cycle stacks.

As a subsequent step, we further extend the methodology to analyze sets of parallel workloads using statistical data analysis, and perform a workload characterization to understand behavioral differences across benchmark suites. We analyze the SPLASH-2, PARSEC and Rodinia benchmark suites and we conclude that the three benchmark suites cover similar areas in the workload space, however, some of the Rodinia benchmarks are highly floating-point compute-intensive; some of the Rodinia and SPLASH-2 benchmarks are highly memory-intensive; and a few PARSEC benchmarks are control flow-intensive.