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PEANO Workshop

Peano is an open source PDE solver framework developed at Technische Universität München. It is based upon the fact that spacetrees, a generalisation of the classical octree concept, yield a cascade of adaptive Cartesian grids.

The goal of the workshop is to give an understanding of the PEANO framework and what can be accomplished when adopting it.

In the first part of the workshop three PEANO developers will present the framework, and the simulations they run. In the second part, people from the Intel Exascience lab will present their implementation of a parallel CG solver, a Particle in Cell solver and a Maxwell solver with PEANO.

The algorithm, called pipelined GMRES, is described in detail in our report (ExaScience report number 04.2012.1 available from our publications page). The method achieves good scalability by removing the expensive global synchronization points from standard GMRES. Impressive speedups have been observed for strong scaling experiments.

Thanks to Jed Brown for the actual PETSc implementation.

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Patus: A Code Generation and Auto-Tuning Framework for Stencil Kernels on Modern Microarchitectures

Matthias Christen (Università della Svizzera italiana, Lugano, Switserland)

Patus is a code generation and auto-tuning framework for the class of stencil computations targeted at modern multi- and many-core processors, such as multicore CPUs and graphics processing units. The ultimate goals of the framework are productivity, portability (of both the code and performance),and achieving a high performance on the target platform.
The key ingredients to achieve the goals of productivity, portability, and performance are domain specific languages (DSLs) and the auto-tuning methodology.
The Patus stencil specification DSL allows the programmer to express a stencil computation in a concise way independently of hardware architecture-specific details. Thus, it increases the programmer productivity by disburdening her or him of low level programming model issues and of manually applying hardware platform-specific code optimization techniques. The use of domain specific languages also implies code reusability: once implemented,the same stencil specification can be reused on different hardware platforms, i.e., the specification code is portable across hardware architectures. Constructing the language to be geared towards a special purpose makes it amenable to more aggressive optimizations and therefore to potentially higher performance.
Auto-tuning provides performance and performance portability by automated adaptation of implementation-specific parameters to the characteristics of the hardware on which the code will run. By automating the process of parameter tuning, the system can also be used more productively than if the programmer had to fine-tune the code manually.

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Speedup your Stencil!

Hans Pabst (Intel)

Stencil-based algorithms are building blocks of numerous applications e.g., seismic exploration and signal processing. The presentation reports the experiences made by implementing “Speedup”, a benchmark that tries current stencil techniques. An overview of current publications gives the background for some of today’s techniques. The focus of the case study is on high-level programming models and runtimes (OpenMP*, Intel Compiler, Intel Cilk Plus, and Intel Threading Building Blocks) up to software auto-tuning and other tools. The study evaluates multicore readiness (threading and SIMD vectorization) with respect to scientists and engineers who do not want to compromise a certain level of algorithmic abstraction, to write Intrinsics, to deal with non-uniform memory (NUMA), or to become an expert with native operating system (OS) threads. The performance results of each of the programming models is given and translated into hints rather than hinting on one or the other model. The talk closes with an outlook to Intel hardware and software developments (Intel Many Integrated Core architecture).

About the Speaker

Hans is a senior technical consultant engineer at Intel Corporation (SSG/DPD). He enables customers in the EMEA region to make use of Intel software developer products (performance libraries, compilers and tools).  Hans’ focus is on parallel algorithms and programming models that target HPC and  scientific applications (engineering). Before he joined RapidMind Inc. of Canada (acquired by Intel), Hans was part of the Virtual Reality Systems Group of Bauhaus University Weimar (Germany). Hans holds a Diploma in Civil Engineering and Computer Science (Dipl.-Ing.).

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Overcoming the Barriers to Exascale through Innovation

Steve Pawlowski (Intel Senior Fellow & CTO Datacenter and Connected Systems Group)

In a period of just 20 years, the performance of the world’s fastest computers has increased by a factor of one million. Although in the past this was due above all to an increase in the processors’ clock frequency, today the performance of top systems is based on a gigantic number of processors operating in parallel. The next target exascale with a thousand times the performance of current systems requires a paradigm shift. The many millions or billions of processor cores must be synchronized, the reliability of the components must be guaranteed, and new storage technologies are required. A quite decisive part will be played by reducing energy consumption.
In his talk, Stephen S. Pawlowski will discuss the unique challenges posed by exascale computing as well as the laboratory partnerships that Intel is developing in the US and Europe. The four labs, including the ExaScience Lab in Leuven, collaborate closely on developing novel algorithms, system architectures and software tools to reach exascale.

The Fault-Tolerance for HPC at Extreme Scale (FTXS 2012) Workshop is solliciting submissions related to dealing with failures, from papers describing innovative ideas over experience reports to extended abstracts proposing disruptive ideas.

More details can be found on FTXS’s website, or in the call for papers in pdf or text formats. Feel free to distribute this information widely so we can get a lively workshop.

CALL FOR PAPERS

2nd International Workshop on Fault-Tolerance for HPC at Extreme Scale (FTXS 2012)

In conjunction with:
The 42nd Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN 2012), Boston, Massachusetts, USA on June 25-28, 2012.

WORKSHOP MOTIVATION

For the HPC community, a new scaling in numbers of processing elements has superseded the historical trend of Moore’s Law scaling in processor frequencies. This progression from single core to multi-core and many-core will be further complicated by the community’s immanent migration from traditional homogeneous architectures to ones that are heterogeneous in nature. As a consequence of these trends, the HPC community is facing rapid increases in the number, variety, and complexity of components, and must thus overcome increases in aggregate fault rates, fault diversity, and complexity of isolating root cause.

Recent analyses demonstrate that HPC systems experience simultaneous (often correlated) failures. In addition, statistical analyses suggest that silent soft errors can not be ignored anymore, because the increase of components, memory size and data paths (including networks) make the probability of silent data corruption (SDC) non-negligible. The HPC community has serious concerns regarding this issue and application users are less confident that they can rely on a correct answer to their computations. Other studies have indicated a growing divergence between failure rates experienced by applications and rates seen by the system hardware and software. At Exascale, some scenarios project failure rates reaching one failure per hour. This conflicts with the current checkpointing approach to fault tolerance that requires up to 30 minutes to restart a parallel execution on the largest systems.  Lastly, stabilization periods for the largest systems are already significant, and the possibility that these could increase in length is of great concern.  During the Approaching Exascale report at SC11, DOE program managers identified resilience as a black swan – the most difficult under-addressed issue facing HPC.

OPEN QUESTIONS

What does the fault-tolerance community need to do in order to be prepared to face the challenges of extreme scale computing? What is needed to keep applications with billions of threads of parallelism up and running on systems that fail tens of times per day? As models predict less than 50% efficiency of traditional checkpoint/restart methods on future systems, are we ready to pay the cost of full redundancy, effectively performing redundant multi-threading (RMT) across entire systems? Do we even have the infrastructure necessary to implement an RMT strategy?

How is the supercomputing community going to efficiently isolate failures on enormously complex systems? Is there any chance to understand these systems in such a way that some failure could be predicted with enough accuracy and anticipation to trigger useful failure avoidance actions? What can the community do to protect applications from SDC in memory and logic? How far the user and the programmer should be involved in managing faults? What are the most promising self-healing numerical methods?

GOALS

The goals of this workshop are to consider these complex questions, to discuss the unique limitations that extreme scale and complexity impose on traditional methods of fault-tolerance, and to explore new strategies for dealing with those challenges.

PAPER SUBMISSIONS

Submissions are solicited in the following categories:

• Regular papers presenting innovative ideas improving the state of the art.
• Experience papers discussing the issues seen on existing extreme-scale systems, including some form of analysis and evaluation.
• Extended abstracts proposing disruptive ideas in the field, including some form of preliminary results

Submissions shall be sent electronically, must conform to IEEE conference proceedings style and should not exceed six pages including all text, appendices, and figures.

All papers will be published, as workshop papers, in the DSN 2012 proceedings and on IEEE Xplore.

TOPICS

Assuming hardware and software errors will be inescapable at extreme
scale, this workshop will consider aspects of fault tolerance peculiar
to extreme scale that include, but are not limited to:

• Quantitative assessments of cost in terms of power, performance, and resource impacts of fault-tolerant techniques, such as checkpoint restart, that are redundant in space, time or information
• Novel fault-tolerance techniques and implementations of emerging hardware and software technologies that guard against silent data corruption (SDC) in memory, logic, and storage and provide end-to-end data integrity for running applications; Studies of hardware / software tradeoffs in error detection, failure prediction, error preemption, and recovery
• Advances in monitoring, analysis, and control of highly complex systems
• Highly scalable fault-tolerant programming models
• Metrics and standards for measuring, improving and enforcing the need for and effectiveness of fault-tolerance
• Failure modeling and scalable methods of reliability, availability, performability and failure prediction for fault-tolerant HPC systems
• Scalable Byzantine fault tolerance and security from single-fault and fail-silent violations
• Benchmarks and experimental environments, including fault-injection and accelerated lifetime testing, for evaluating performance of resilience techniques under stress

IMPORTANT DATES

Submission of papers:   March 16, 2012
Author notification:    April 6, 2012
Camera ready papers:    April 27, 2012
Workshop:               June 25, 2012

WORKSHOP ORGANIZERS

Nathan DeBardeleben – Los Alamos National Laboratory
Jon Stearley – Sandia National Laboratories
Franck Cappello – INRIA & University of Illinois at Urbana Champaign

PROGRAM COMMITTEE

George Bosilca – University of Tennessee, Knoxville
Greg Bronevetsky – Lawrence Livermore National Laboratory
John Daly – Department of Defense
Christian Engelmann – Oak Ridge National Laboratory
Kurt Ferreira – Sandia National Laboratories
Ana Gainaru – University of Illinois, Urbana-Champaign
Hideyiki Jitsumoto – University of Tokyo
Zbigniew Kalbarczyk – University of Illinois, Urbana-Champaign
Rakesh Kumar – University of Illinois, Urbana-Champaign
Zhiling Lan – Illinois Institute of Technology
Yve Robert – ENS Lyon
Roel Wuyts – Intel ExaScience Lab, Leuven, Belgium and KU Leuven (Leuven, Belgium)
Felix Salfner – SAP Innovation Center Potsdam
Mitsuhisa Sato – University of Tsukuba
Stephen Scott – Oak Ridge National Laboratory and Tennessee Tech University

See http://institute.lanl.gov/resilience/workshops/ftxs2012/
and http://2012.dsn.org for more information.