Architectural Simulation

Due to the way hardware technologies are evolving, future machines will have to cope with new constraints such as extreme energy efficiency and resilience to faulty components. These changes require us to rethink traditional computer architectures and software organizations. Architectural simulation is an indispensable tool for this as it enables today’s designers to predict what the performance, power efficiency and reliability will be for tomorrow’s machines.

Fast and accurate simulation

Traditional microarchitectural simulation is very detailed, yet very slow, and will not scale towards simulating a machine with millions of cores and possibly billions of software threads. We are working on ways to increase the level of abstraction of hardware simulation, while incorporating techniques to make statements both about energy efficiency and reliability metrics. This allows one to work toward the optimization of HPC software for the life sciences while they interact with future forms of hardware.

Sniper multi-core simulator

A public version of Sniper, our architectural simulator, is freely available for academic research, and can be downloaded at It is designed for studying node-level hardware and software performance. Sniper has been validated, shows good accuracy compared to actual hardware, and can simulate systems with tens of cores at simulation speeds of up to 3 MIPS on recent multi-core host machines.

Workload reduction

In addition to node-level behavior, we are now looking at new ways to make predictions about the complete system. Some future directions include simulation and emulation of multi-node systems, using versions of the workload that are reduced in both in space and in time (scale-down). This reduction will allow the next-generation software to be analyzed using today’s systems. Additionally, we will use techniques to extrapolate utilization, performance, power and reliability for these large-scale systems (scale-up).


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